In a data sending and receiving system, it is needed to generate a clock at a receive end, which is synchronized with that at a transmit end, so as to ensure communication. Before sending data, the transmit end first sends a string of synchronization clock pulses to the receive end, and the receive end locks a receiving frequency of the receive end according to a clock pulse frequency and a time sequence by using a frequency tracking system, so as to remain synchronized with the transmit end throughout a process of data receiving.
In the prior art, a double-loop frequency tracking system is generally used to perform frequency tracking on a synchronization clock sent by the transmit end. As shown in FIG. 1, FIG. 1 is a structure diagram of a double-loop frequency tracking system. In FIG. 1, a first clock signal of a numerically controlled oscillator enters a first phase-locked loop; after the first clock signal passes through a first time-to-digital converter, the first time-to-digital converter generates a phase signal according to an input reference clock signal; and a first phase detector and a first filter adjust a frequency of the first clock signal output by the numerically controlled oscillator, so that the frequency of the first clock signal is equal to a frequency of a second clock signal received by a receive end. The first phase-locked loop is generally implemented by an analog method, causing a relatively great error; therefore, a second loop needs to be added outside the first phase-locked loop to track the second clock signal. After the first clock signal enters a second time-to-digital converter of a second phase-locked loop, the second time-to-digital converter generates a phase signal according to the second clock signal, and a second phase detector and a second filter adjust a phase of the first clock signal output by the numerically controlled oscillator, so that the phase of the first clock signal is equal to a phase of the second clock signal, and the error is reduced.
An existing time-to-digital converter includes an array formed by multiple buffers and an array formed by multiple triggers, a clock output by the numerically controlled oscillator passes through each buffer and is transferred backwards, and an output end of each buffer is used as a phase detection point of a trigger array. A frequency of the clock output by the numerically controlled oscillator is relatively high, to achieve frequency coverage, a larger quantity of buffers are required, and correspondingly, a larger quantity of triggers are required; therefore, using two time-to-digital converters may increase energy consumed by the system. In addition, affected by the quantity of buffers and the quantity of triggers, an occupied area of the system is accordingly increased, manufacturing costs are increased, and complexity of system design is also increased.